Utility Vector Logic - 2021.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator

Document ID
Release Date
2021.2 English

This IP can be configured for different logic modes and input widths. The supported logic operations are AND, OR, XOR, and NOT. The C_Size is the vector size of the input and output signals, and can be 1 or more. As an example, if the IP is configured in the AND mode and C Size is set to 4, then the resulting logic would consist of 4 parallel, 2-input AND gates.

If the IP is configured as an inverter or NOT, then the C_Size denotes the number of single bit inverters. See the LogiCORE IP Utility Vector Logic Product Brief (PB046) for more information.

Figure 1. Utility Vector Logic IP Dialog Box