Final I/O Validation with an Implemented Design - 2021.2 English

Vivado Design Suite User Guide: I/O and Clock Planning

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2021.2 English

You must use a fully implemented design to validate the final valid I/O pinout and clock configuration. Proper clock resource validation requires fully routed implementation of all clocks. You can examine the implementation reports for I/O and clock-related messages. Finally, double-check the I/O port assignments with the PCB designer to ensure that the FPGA is correctly defined for the system-level design.

Note that I/O placement and location is highly dependent on the clock placement and what nibble the clock comes into. See Versal ACAP SelectIO Resources Architecture Manual (AM010) and Versal ACAP Clocking Resources Architecture Manual (AM003) for more information about clocking in I/O.