Creating Single-Ended or Differential I/O Ports - 2021.2 English

Vivado Design Suite User Guide: I/O and Clock Planning
Document ID
UG899
Release Date
2021-11-10
Version
2021.2 English
You can manually define new ports in an I/O planning project. Refer to Xilinx device documentation for information regarding voltage capabilities of the device.
Note: The I/O Ports window groups each differential pair into a single row. Because a single row represents two ports, the total number of ports shown in parentheses is higher than the number of rows. To get a list of signals that matches the total number of ports in the I/O Ports window, enter the following Tcl command: 
get_ports * -filter {BUS_WIDTH == "" }

To create I/O ports:

  1. In the I/O Ports window, right-click, and select Create I/O Ports.
  2. In the Create I/O Ports dialog box, edit the following options, and click OK:
    Name
    Enter the port or bus name to create.
    Direction
    Select the port direction.
    Diff Pair
    Define differential pair signals or buses.
    Note: To create a differential I/O port, enable this option. This creates two ports and adds a _N suffix to the name of the negative port.
    Create Bus
    Enter a bus range for bus creation.
    I/O Standard
    Select the I/O standard constraint.
    Drive Strength
    Select the drive strength value.
    Slew Type
    Select the slew type value.
    Pull Type
    Select the pull type value.
    In Term Type
    Define the parallel termination properties of the input signal.
Figure 1. Create I/O Ports Dialog Box