Primitive: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
Introduction
The IBUFDS_DIFF_OUT_IBUFDISABLE primitive shown is a differential input buffer with complementary differential outputs. The USE_IBUFDISABLE attribute must be set to TRUE and the SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Diff_p Buffer Input. Connect to top-level p-side input port. |
IB | Input | 1 | Diff_n Buffer Input. Connect to top-level n-side input port. |
IBUFDISABLE | Input | 1 | The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'. |
O | Output | 1 | Buffer diff_p output |
OB | Output | 1 | Buffer diff_n output |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DEVICE | STRING | "VERSAL_PRIME", "VERSAL_PRIME_ES1", "VERSAL_PRIME_ES2" | "7SERIES" | Set the device version for simulation functionality. |
USE_IBUFDISABLE | STRING | "TRUE", "FALSE", "T_CONTROL" | "TRUE" | This attribute must be unspecified or set to "TRUE" if specified. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
-- Versal Prime series
-- Xilinx HDL Language Template, version 2021.2
IBUFDS_DIFF_OUT_IBUFDISABLE_inst : IBUFDS_DIFF_OUT_IBUFDISABLE
generic map (
SIM_DEVICE => "VERSAL_PRIME" -- Set the device version for simulation functionality (VERSAL_PRIME,
-- VERSAL_PRIME_ES1)
)
port map (
O => O, -- 1-bit output: Buffer diff_p output
OB => OB, -- 1-bit output: Buffer diff_n output
I => I, -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
IB => IB, -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
IBUFDISABLE => IBUFDISABLE -- 1-bit input: Must be tied to a logic '0'
);
-- End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation
Verilog Instantiation Template
// IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
// Versal Prime series
// Xilinx HDL Language Template, version 2021.2
IBUFDS_DIFF_OUT_IBUFDISABLE #(
.SIM_DEVICE("VERSAL_PRIME") // Set the device version for simulation functionality (VERSAL_PRIME,
// VERSAL_PRIME_ES1)
)
IBUFDS_DIFF_OUT_IBUFDISABLE_inst (
.O(O), // 1-bit output: Buffer diff_p output
.OB(OB), // 1-bit output: Buffer diff_n output
.I(I), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
.IB(IB), // 1-bit input: Diff_n buffer input (connect directly to top-level port)
.IBUFDISABLE(IBUFDISABLE) // 1-bit input: Must be tied to a logic '0'
);
// End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)