Primitive: Differential Input Buffer with Offset Calibration
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
Introduction
The differential input buffer (IBUFDSE3) primitive is only supported in XP I/O banks. This primitive has functions similar to the IBUFDS_IBUFDISABLE along with controls for offset calibration and input buffer disable (IBUFDISABLE). The offset calibration feature is accessed using the OSC_EN and OSC[3:0] ports. The VREF scan feature is not supported with this primitive.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied in XDC or to the top-level port via an appropriate property. For details on applying such properties to XDC or the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
I | Input | 1 | Diff_p Buffer Input. Connect to top-level p-side input port. |
IB | Input | 1 | Diff_n Buffer Input. Connect to top-level n-side input port. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time. |
O | Output | 1 | Buffer output |
OSC<3:0> | Input | 4 | Offset cancellation value |
OSC_EN<1:0> | Input | 2 | Offset cancellation enable. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DEVICE | STRING | "VERSAL_PRIME", "VERSAL_PRIME_ES1", "VERSAL_PRIME_ES2" | "ULTRASCALE" | Set the device version for simulation functionality. |
SIM_INPUT_BUFFER_OFFSET | DECIMAL | -50 to 50 | 0 | Offset value for simulation purposes. |
USE_IBUFDISABLE | STRING | "FALSE", "T_CONTROL", "TRUE" | "FALSE" | Set this attribute to "TRUE" to enable the IBUFDISABLE pin. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDSE3: Differential Input Buffer with Offset Calibration
-- Versal Prime series
-- Xilinx HDL Language Template, version 2021.2
IBUFDSE3_inst : IBUFDSE3
generic map (
SIM_DEVICE => "VERSAL_PRIME", -- Set the device version for simulation functionality (VERSAL_PRIME,
-- VERSAL_PRIME_ES1)
SIM_INPUT_BUFFER_OFFSET => 0, -- Offset value for simulation (-50-50)
USE_IBUFDISABLE => "FALSE" -- Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
port map (
O => O, -- 1-bit output: Buffer output
I => I, -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
IB => IB, -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
IBUFDISABLE => IBUFDISABLE, -- 1-bit input: Buffer disable input, high=disable
OSC => OSC, -- 4-bit input: Offset cancellation value
OSC_EN => OSC_EN -- 2-bit input: Offset cancellation enable
);
-- End of IBUFDSE3_inst instantiation
Verilog Instantiation Template
// IBUFDSE3: Differential Input Buffer with Offset Calibration
// Versal Prime series
// Xilinx HDL Language Template, version 2021.2
IBUFDSE3 #(
.SIM_DEVICE("VERSAL_PRIME"), // Set the device version for simulation functionality (VERSAL_PRIME,
// VERSAL_PRIME_ES1)
.SIM_INPUT_BUFFER_OFFSET(0), // Offset value for simulation (-50-50)
.USE_IBUFDISABLE("FALSE") // Enable/Disable the IBUFDISABLE pin (FALSE, TRUE, T_CONTROL)
)
IBUFDSE3_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Diff_p buffer input (connect directly to top-level port)
.IB(IB), // 1-bit input: Diff_n buffer input (connect directly to top-level port)
.IBUFDISABLE(IBUFDISABLE), // 1-bit input: Buffer disable input, high=disable
.OSC(OSC), // 4-bit input: Offset cancellation value
.OSC_EN(OSC_EN) // 2-bit input: Offset cancellation enable
);
// End of IBUFDSE3_inst instantiation
Related Information
- Versal ACAP SelectIO Resources Architecture Manual (AM010)