Primitive: Digital Phase-Locked Loop (DPLL)
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
Introduction
The DPLL is an all-digital phase locked loop that is located next to the HDIO column, the GT clocking column, and co-located in the same clocking tile as as the MMCMs. DPLLs can perform frequency synthesis, clock network deskew, and jitter filtering for internal and external clocks. DPLLs have some limitations in operation versus other clock modifying blocks such as the XPLLs and MMCMs.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLKFB_DESKEW | Input | 1 | Secondary (feedback) clock input to the phase detector block for deskewing clock network delays. |
CLKIN | Input | 1 | Input Clock. |
CLKIN_DESKEW | Input | 1 | Primary clock input to the phase detector block for deskewing clock network delays between two different CLKOUT networks. |
CLKOUT0 | Output | 1 | General clock output CLKOUT0. Generally connected to a global buffer. |
CLKOUT1 | Output | 1 | General clock output CLKOUT1. Generally connected to a global buffer. |
CLKOUT2 | Output | 1 | General clock output CLKOUT2. Generally connected to a global buffer. |
CLKOUT3 | Output | 1 | General clock output CLKOUT3. Generally connected to a global buffer. |
DADDR<6:0> | Input | 7 | The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. |
DCLK | Input | 1 | The DCLK signal is the reference clock for the dynamic reconfiguration port. |
DEN | Input | 1 | The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. |
DI<15:0> | Input | 16 | The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. |
DO<15:0> | Output | 16 | The dynamic reconfiguration output bus provides DPLL data output when using dynamic reconfiguration |
DRDY | Output | 1 | The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the DPLLs dynamic reconfiguration feature. |
DWE | Input | 1 | The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. |
LOCKED | Output | 1 | The LOCKED signal indicates that all functions requiring a LOCKED signal for the DPLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB and LOCKED_DESKEW if used. |
LOCKED_DESKEW | Output | 1 | Indicates if the deskew circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits. |
LOCKED_FB | Output | 1 | An output from the DPLL that indicates when the DPLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The DPLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The DPLL must be reset after LOCKED is deasserted. |
PSCLK | Input | 1 | Phase shift clock. |
PSDONE | Output | 1 | Phase shift done. |
PSEN | Input | 1 | Phase shift enable. |
PSINCDEC | Input | 1 | Phase shift increment/decrement control. |
PWRDWN | Input | 1 | Powers down instantiated but unused DPLLs. |
RST | Input | 1 | Asynchronous reset signal. The RST signal is an asynchronous reset for the DPLL. The DPLL synchronously re-enables itself when this signal is released (that is, DPLL re-enabled). A reset is required when the input clock conditions change (for example, frequency). |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
CLKFBOUT_FRACT | DECIMAL | 0 to 63 | 0 | 6-bit fractional M feedback divider in increments of 1/63. Generates a fraction of the CLKFBOUT_MULT value and adds it to CLKFBOUT_MULT. |
CLKFBOUT_MULT | DECIMAL | 10 to 400 | 42 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. |
CLKIN_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period in ns to the DLL CLKIN input. |
CLKOUT0_DIVIDE | DECIMAL | 2 to 511 | 2 | Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT0_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT0 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT0_DIVIDE) / 8 |
CLKOUT0_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 | CLKOUT0 counter variable fine phase shift or deskew select
Note: Other binary values are not valid.
|
CLKOUT1_DIVIDE | DECIMAL | 2 to 511 | 2 | Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT1_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT1 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT1_DIVIDE) / 8 |
CLKOUT1_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 |
Note: Other binary values are not valid.
|
CLKOUT2_DIVIDE | DECIMAL | 2 to 511 | 2 | Specifies the amount to divide the CLKOUT2 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT2_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT2 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT2_DIVIDE) / 8 |
CLKOUT2_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 |
Note: Other binary values are not valid.
|
CLKOUT3_DIVIDE | DECIMAL | 2 to 511 | 2 | Specifies the amount to divide the CLKOUT3 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency. |
CLKOUT3_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT3 output. In static phase shift mode, the minimum phase step resolution (degrees) = (360 / CLKOUT3_DIVIDE) / 8 |
CLKOUT3_PHASE_CTRL | BINARY | 2'b00 to 2'b11 | 2'b00 |
Note: Other binary values are not valid.
|
DESKEW_DELAY | DECIMAL | 0 to 63 | 0 | Value of the optional programmable delay in the deskew circuit. |
DESKEW_DELAY_EN | STRING | "FALSE", "TRUE" | "FALSE" | Set to TRUE to enabled the optional programmable delay in the deskew circuit. |
DESKEW_DELAY_PATH | STRING | "FALSE", "TRUE" | "FALSE" | Determines if the CLKIN_DESKEW path or the CLKFB_DESKEW path is selected for the optional programmable delay. TRUE = CLKFB_DESKEW, FALSE = CLKIN_DESKEW. |
DIVCLK_DIVIDE | DECIMAL | 1 to 123 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD. |
IS_CLKFB_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFB_DESKEW pin. |
IS_CLKIN_DESKEW_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN_DESKEW pin. |
IS_CLKIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN pin. |
IS_PSEN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSEN pin. |
IS_PSINCDEC_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PSINCDEC pin. |
IS_PWRDWN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PWRDWN pin. |
IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
LOCK_WAIT | STRING | "FALSE", "TRUE" | "FALSE" | Wait during the configuration for the startup for the DPLL to lock. |
PERF_MODE | STRING | "LIMITED", "FULL" | "LIMITED" | Specifies DPLL performance mode. Must remain at the default setting ("LIMITED") where deskew mode is defeatured. All other values are reserved for Xilinx IP use only. |
REF_JITTER | 3 significant digit FLOAT | 0.000 to 0.200 | 0.010 | Allows the specification of the expected jitter on the reference clock to better optimize DPLL performance. If known, the value provided should be specified in terms of unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock. |
ZHOLD | STRING | "FALSE", "TRUE" | "FALSE" | Indicates the DPLL is configured to provide a negative hold time at the HDIO registers. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DPLL: Digital Phase-Locked Loop (DPLL)
-- Versal Prime series
-- Xilinx HDL Language Template, version 2021.2
DPLL_inst : DPLL
generic map (
CLKFBOUT_FRACT => 0, -- 6-bit fraction M feedback divider (0-63)
CLKFBOUT_MULT => 42, -- Multiply value for all CLKOUT, (10-400)
CLKIN_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
CLKOUT0_DIVIDE => 2, -- Divide amount for CLKOUT0 (2-511)
CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0 (-360.000-360.000)
CLKOUT0_PHASE_CTRL => "00", -- CLKOUT0 fine phase shift or deskew select (0-11)
CLKOUT1_DIVIDE => 2, -- Divide amount for CLKOUT1 (2-511)
CLKOUT1_PHASE => 0.0, -- Phase offset for CLKOUT1 (-360.000-360.000)
CLKOUT1_PHASE_CTRL => "00", -- CLKOUT1 fine phase shift or deskew select (0-11)
CLKOUT2_DIVIDE => 2, -- Divide amount for CLKOUT2 (2-511)
CLKOUT2_PHASE => 0.0, -- Phase offset for CLKOUT2 (-360.000-360.000)
CLKOUT2_PHASE_CTRL => "00", -- CLKOUT2 fine phase shift or deskew select (0-11)
CLKOUT3_DIVIDE => 2, -- Divide amount for CLKOUT3 (2-511)
CLKOUT3_PHASE => 0.0, -- Phase offset for CLKOUT3 (-360.000-360.000)
CLKOUT3_PHASE_CTRL => "00", -- CLKOUT2 fine phase shift or deskew select (0-11)
DESKEW_DELAY => 0, -- Deskew optional programmable delay
DESKEW_DELAY_EN => "FALSE", -- Enable deskew optional programmable delay
DESKEW_DELAY_PATH => "FALSE", -- Select CLKFB_DESKEW (TRUE) or CLKIN_DESKEW (FALSE)
DIVCLK_DIVIDE => 1, -- Master division value
IS_CLKFB_DESKEW_INVERTED => '0', -- Optional inversion for CLKFB_DESKEW
IS_CLKIN_DESKEW_INVERTED => '0', -- Optional inversion for CLKIN_DESKEW
IS_CLKIN_INVERTED => '0', -- Optional inversion for CLKIN
IS_PSEN_INVERTED => '0', -- Optional inversion for PSEN
IS_PSINCDEC_INVERTED => '0', -- Optional inversion for PSINCDEC
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
LOCK_WAIT => "FALSE", -- Lock wait
PERF_MODE => "LIMITED", -- Leave as default ("LIMITED"). For Xilinx IP use only.
REF_JITTER => 0.0, -- Reference input jitter in UI (0.000-0.200).
ZHOLD => "FALSE" -- Negative hold time at the HDIO registers
)
port map (
CLKOUT0 => CLKOUT0, -- 1-bit output: General Clock output
CLKOUT1 => CLKOUT1, -- 1-bit output: General Clock output
CLKOUT2 => CLKOUT2, -- 1-bit output: General Clock output
CLKOUT3 => CLKOUT3, -- 1-bit output: General Clock output
DO => DO, -- 16-bit output: DRP data output
DRDY => DRDY, -- 1-bit output: DRP ready
LOCKED => LOCKED, -- 1-bit output: LOCK
LOCKED_DESKEW => LOCKED_DESKEW, -- 1-bit output: LOCK DESKEW
LOCKED_FB => LOCKED_FB, -- 1-bit output: LOCK FEEDBACK
PSDONE => PSDONE, -- 1-bit output: Phase shift done
CLKFB_DESKEW => CLKFB_DESKEW, -- 1-bit input: Secondary clock input to PD
CLKIN => CLKIN, -- 1-bit input: Input Clock
CLKIN_DESKEW => CLKIN_DESKEW, -- 1-bit input: Primary clock input to PD
DADDR => DADDR, -- 7-bit input: DRP address
DCLK => DCLK, -- 1-bit input: DRP clock
DEN => DEN, -- 1-bit input: DRP enable
DI => DI, -- 16-bit input: DRP data input
DWE => DWE, -- 1-bit input: DRP write enable
PSCLK => PSCLK, -- 1-bit input: Phase shift clock
PSEN => PSEN, -- 1-bit input: Phase shift enable
PSINCDEC => PSINCDEC, -- 1-bit input: Phase shift increment/decrement
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => RST -- 1-bit input: Reset
);
-- End of DPLL_inst instantiation
Verilog Instantiation Template
// DPLL: Digital Phase-Locked Loop (DPLL)
// Versal Prime series
// Xilinx HDL Language Template, version 2021.2
DPLL #(
.CLKFBOUT_FRACT(0), // 6-bit fraction M feedback divider (0-63)
.CLKFBOUT_MULT(42), // Multiply value for all CLKOUT, (10-400)
.CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(2), // Divide amount for CLKOUT0 (2-511)
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000)
.CLKOUT0_PHASE_CTRL(2'b00), // CLKOUT0 fine phase shift or deskew select (0-11)
.CLKOUT1_DIVIDE(2), // Divide amount for CLKOUT1 (2-511)
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT1 (-360.000-360.000)
.CLKOUT1_PHASE_CTRL(2'b00), // CLKOUT1 fine phase shift or deskew select (0-11)
.CLKOUT2_DIVIDE(2), // Divide amount for CLKOUT2 (2-511)
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT2 (-360.000-360.000)
.CLKOUT2_PHASE_CTRL(2'b00), // CLKOUT2 fine phase shift or deskew select (0-11)
.CLKOUT3_DIVIDE(2), // Divide amount for CLKOUT3 (2-511)
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT3 (-360.000-360.000)
.CLKOUT3_PHASE_CTRL(2'b00), // CLKOUT2 fine phase shift or deskew select (0-11)
.DESKEW_DELAY(0), // Deskew optional programmable delay
.DESKEW_DELAY_EN("FALSE"), // Enable deskew optional programmable delay
.DESKEW_DELAY_PATH("FALSE"), // Select CLKFB_DESKEW (TRUE) or CLKIN_DESKEW (FALSE)
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFB_DESKEW_INVERTED(1'b0), // Optional inversion for CLKFB_DESKEW
.IS_CLKIN_DESKEW_INVERTED(1'b0), // Optional inversion for CLKIN_DESKEW
.IS_CLKIN_INVERTED(1'b0), // Optional inversion for CLKIN
.IS_PSEN_INVERTED(1'b0), // Optional inversion for PSEN
.IS_PSINCDEC_INVERTED(1'b0), // Optional inversion for PSINCDEC
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.LOCK_WAIT("FALSE"), // Lock wait
.PERF_MODE("LIMITED"), // Leave as default ("LIMITED"). For Xilinx IP use only.
.REF_JITTER(0.0), // Reference input jitter in UI (0.000-0.200).
.ZHOLD("FALSE") // Negative hold time at the HDIO registers
)
DPLL_inst (
.CLKOUT0(CLKOUT0), // 1-bit output: General Clock output
.CLKOUT1(CLKOUT1), // 1-bit output: General Clock output
.CLKOUT2(CLKOUT2), // 1-bit output: General Clock output
.CLKOUT3(CLKOUT3), // 1-bit output: General Clock output
.DO(DO), // 16-bit output: DRP data output
.DRDY(DRDY), // 1-bit output: DRP ready
.LOCKED(LOCKED), // 1-bit output: LOCK
.LOCKED_DESKEW(LOCKED_DESKEW), // 1-bit output: LOCK DESKEW
.LOCKED_FB(LOCKED_FB), // 1-bit output: LOCK FEEDBACK
.PSDONE(PSDONE), // 1-bit output: Phase shift done
.CLKFB_DESKEW(CLKFB_DESKEW), // 1-bit input: Secondary clock input to PD
.CLKIN(CLKIN), // 1-bit input: Input Clock
.CLKIN_DESKEW(CLKIN_DESKEW), // 1-bit input: Primary clock input to PD
.DADDR(DADDR), // 7-bit input: DRP address
.DCLK(DCLK), // 1-bit input: DRP clock
.DEN(DEN), // 1-bit input: DRP enable
.DI(DI), // 16-bit input: DRP data input
.DWE(DWE), // 1-bit input: DRP write enable
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
.PSEN(PSEN), // 1-bit input: Phase shift enable
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
// End of DPLL_inst instantiation
Related Information
- Versal ACAP Clocking Resources Architecture Manual (AM003)