Primitive: DDR4 memory controller Register Interface Unit
- PRIMITIVE_GROUP: ADVANCED
- PRIMITIVE_SUBGROUP: BUFFER
Introduction
The DDRMC is the DDR4 memory controller Register Interface Unit block in Versal devices. This element is not intended to be instantiated, used, or modified outside of Xilinx-generated IP.
Design Entry Method
| Instantiation | No |
| Inference | No |
| IP and IP Integrator Catalog | No |
Related Information
- Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)