Adding Design Sources - 2021.1 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
Release Date
2021.1 English
  1. Select File > Add Sources.
    Note: Alternatively, you can click Add Sources in the Flow Navigator, or select Add Sources from the right-click menu in the Sources window.
  2. In the Add Sources wizard, select Add or Create Design Sources, and click Next.
  3. In the Add or Create Design Sources page, set the following options, and click Finish.
    Add Files
    Opens a file browser so you can select files to add to the project. You can add the following file types to an RTL project: HDL, EDIF, NGC, BMM, ELF, DCP, and other file types.
    Note: In the Add Source Files dialog box, each file or directory is represented by an icon indicating it as a file or folder. A small red square indicates it is read only.
    Add Directories
    Opens a directory browser to add source files from the selected directories. Files in the specified directory with valid source file extensions are added to the project.
    Create File
    Opens the Create Source File dialog box in which you can create new VHDL, Verilog, Verilog header, or SystemVerilog files.
    Specify the RTL library for a single file, or the files in a directory, by selecting a library from the currently defined library names, or specify a new library name by typing in the Library text field.
    Note: This option applies to VHDL files only. By default, HDL sources are added to the xil_defaultlib library. You can create or reference additional user VHDL libraries as needed. For Verilog and SystemVerilog files, leave the library set to xil_defaultlib.
    Removes the selected source files from the list of files to be added.
    Move Up / Move Down
    Moves the file or directory up/down in the list order. The order of the files affects the order of elaboration and compilation during downstream processes such as synthesis and simulation. See Specifying the Top Module and Reordering Source Files.
    Scan and Add RTL Include Files into Project
    Scans the added RTL files and adds any referenced Verilog 'include files into the local project directory structure.
    Copy Sources into Project
    Copies files into the local project directory instead of referencing the original files.
    Note: If you added directories of source files using Add Directories, the directory structure is maintained when the files are copied locally into the project. For more information, see Using Remote Sources or Copying Sources into Project.
    Add Sources from Subdirectories
    Adds source files from the subdirectories of directories specified using the Add Directories option.