Using Xilinx Parameterized Macros - 2021.1 English

Vivado Design Suite User Guide System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2021-06-16
Version
2021.1 English

XPMs are simple customizable solutions for common use cases in an HDL flow, such as RAM or ROM, clock domain crossings, and FIFOs. XPMs are SystemVerilog HDL code delivered with the Vivado Design Suite, and can be found in the ./data/ip/xpm folder of the software installation. They can be thought of as parameterized IP, with default values for parameters that can be changed to meet design requirements.

The types of XPMs include:

  • XPM_MEMORY with various RAM and ROM memory structures
  • XPM_CDC with various safe Clock Domain Crossing (CDC) logic implementations
  • XPM_FIFO for synchronous and asynchronous FIFO structures