The <connections> section defines the connections between different components. The <connection> tag identifies two components associated with a connection. The <connection_map> tag describes the bus connection between the two components. The details of a <connection> are used by the Vivado Design Suite to look up corresponding constraints in the part0_pins.xml file when one of the components is the FPGA type <component>.
<connections>
<connection name="part0_dip" component1="part0" component2="dip_switches">
<connection_map name="part0_dip_1" typical_delay="5" c1_st_index="0"
c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
</connection>
</connections>A <connection> can have the following attributes:
| Tag | Usage/Description | Example (KC705) |
|---|---|---|
| name= | Name given to the connection. | part0_dip |
| component1= | The first component in the connection. | part0 |
| component2= | The second component in the connection. | dip_switches |
The <connection_map> has the following attributes:
| Tag | Usage/Description | Example (KC705) |
|---|---|---|
| typical_delay= | The delay on the connection between components. | 5 |
| c1_st_index= |
This is the <pin> index of the starting pin in the connection for component1. If component1 is an FPGA, this index is taken from the part0_pins.xml file. |
0 |
| c1_end_index= | This is the <pin> index of the final pin in the connection for component1. | 3 |
| c2_st_index= | This is the <pin> index of the starting pin for component2. | 0 |
| c2_end_index= | This is the <pin> index of the final pin in the connection for component2. | 3 |