Creating an RTL Project - 2021.1 English

An RTL project may have RTL, Block Design, IP and/or RTL sources. This dialog lets you specify which sources to add during project creation. Addition files can be added later during RTL code development, analysis as well as synthesis and implementation. For more information on RTL development and analysis, see Elaborating the RTL Design.

1. Follow the steps in Creating a Project.
2. In the Project Type page, select RTL Project, and click Next.
   Note: If necessary, you can select Do not specify sources at this time. This skips the steps of adding design sources and enables you to select the target part and create the project.
   Note: Extensible platforms are used by Vitis software platform to incorporate software kernels. Setting this project property enables platform properties to add interfaces which can then be augmented by Vitis software platform. For more information on extensible platforms, see Creating Embedded Platforms in Vitis.
3. In the Add Sources page, set the following options, and click Next:

   Add Files

   Opens a file browser so you can select files to add to the project. You can add the following file types to an RTL project: Verilog, VHDL, SystemVerilog, BD, XCI, EDIF, NGC, BMM, ELF, and other file types.

   Note: In the Add Source Files dialog box, each file or directory is represented by an icon indicating it as a file or folder. A small red square indicates it is read only.

   Add Directories

   Opens a directory browser to add source files from the selected directories. Files in the specified directory with valid source file extensions are added to the project.

   Add Sources from Subdirectories

   Specifies that the tool should scan the listed directory's directory tree for additional sources.

   Create File

   Opens the Create Source File dialog box in which you can create new VHDL, Verilog, Verilog header, or SystemVerilog files. Create Source File dialog box, set the following options:

   File type

   Specifies one of the following file formats: Verilog file (.v extension), Verilog Header file (.vh extension)., SystemVerilog file (.sv extension), VHDL file (.vhdl extension), or Memory Files (.mem extension).

   File name

   Specifies a name for the new HDL source file.

   File location

   Specifies a location in which to create the file.

   Note: A placeholder for the file is added to the list of sources. The file is created when you click Finish.

   Library

   Specifies the RTL library for a file or directory. You can select a library name, or specify a new library name by typing in the Library text field.

   Note: This option applies to VHDL files only. By default, HDL sources are added to the xil_defaultlib library. You can create or reference additional user VHDL libraries as needed. For Verilog and SystemVerilog files, leave the library set to xil_defaultlib.

   HDL Source for

   Specifies whether the source being loaded is an RTL source file for synthesis and simulation or an RTL test bench for simulation only.

   Remove

   Removes the selected source files from the list of files to be added.

   Move Up / Move Down

   Moves the file or directory up/down in the list order. The order of the files affects the order of elaboration and compilation during downstream processes such as synthesis and simulation.

   Scan and Add RTL Include Files into Project

   Scans all RTL source files and adds any referenced Verilog 'include files into the project structure.

   Copy Sources into Project

   Copies the added source files and include files into the local project directory instead of referencing the original files. If you added directories of source files using Add Directories, the directory structure is maintained when the files are copied locally into the project. For more information, see Using Remote Sources or Copying Sources into Project.

   Add Sources from Subdirectories

   Adds source files from the subdirectories of directories specified with Add Directories.

   Target Language

   Specifies the target language for the design as either Verilog or VHDL. New RTL files default to the specified target language. Output files are generated from the design in the specified target language.

   Simulator Language

   Specifies the language in which output products are generated for simulation as well as the file types used for third party simulation scripts. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).

   Add Sources

   Invokes a file browser so you can select Xilinx Core Instance (XCI) files, which are native to the Vivado Design Suite, a Core Container (XCIX) file, which is a single file representation for an IP, or CORE Generator core (XCO) files. You can also add Block Design files (BD) from the Vivado IP Integrator feature, or Mathworks Simulink project files (SLX or MDL) for DSP sub-designs.

   Figure 1. New Project Wizard—Add Sources Page