WebTalk does not collect your design netlist or any other proprietary information that can be used to reverse engineer your design. The data Xilinx collects through WebTalk includes:
- Software version
- Platform information
For example, operating system, speed and number of processors, and main memory.
- Unique project ID
- Authorization code
- Date of generation
- Targeted device and family information
For more information on the type of data that is collected, see the Xilinx Design Tools WebTalk page. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.xm file in the project directory. You can also open the usage_statistics_webtalk.html file for easy viewing of the data transmitted to Xilinx. Additionally, additional data collection files for sub-flows in the Xilinx tools are also generated which include:
- usage_statistics_ext_xsim.xml
- usage_statistices_ext_labtools.xml
- usage_statistics_ext_vitis.xml
- usage_statistics_ext_petalinux.xml (along with corresponding HTML files)