Part 1: Creating a System Generator Package from Vitis HLS - 2020.2 English

Vivado Design Suite Tutorial: Model-Based DSP Design using Add-on for MATLAB and Simulink (UG1498)
Document ID
UG1498
Release Date
2021-01-22
Version
2020.2 English
  1. Invoke Vitis HLS: Click Start > Xilinx Design Tools > Vitis HLS 2020.2.
  2. Select Open Project in the welcome screen and navigate to the Vitis HLS project directory C:\SysGen_Tutorial\Lab2\C_code\hls_project as shown in the following figure.

  3. Click OK to open the project.
  4. Expand the Source folder in the Explorer pane (left-hand side) and double-click the file MedianFilter.cpp to view the contents of the C++ file as shown in the following figure.

    This file implements a 2-Dimensional median filter on 3x3 window size.

  5. Synthesize the source file by right-clicking on solution1 and selecting C Synthesis > C Synthesis as shown in the following figure.

    When the synthesis completes, Vitis HLS displays this message: 
    Finished C synthesis

    Now you will package the source for use in System Generator.

  6. Right-click solution1 and select Export RTL.
  7. Set Format Selection to Vivado IP for System Generator as shown in the following figure and click OK.

    When the Export RTL process completes, Vitis HLS displays this message:

    Finished export RTL
  8. Exit Vivado HLS.