Lab 4: Working with Multi-Rate Systems - 2020.2 English

Vivado Design Suite Tutorial: Model-Based DSP Design using Add-on for MATLAB and Simulink (UG1498)

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2020.2 English

In this lab exercise, you will learn how to efficiently implement designs with multiple data rates using multiple clock domains.


After completing this lab, you will be able to:

  • Understand the benefits of using multiple clock domains to implement multi-rate designs.
  • Understand how to isolate hierarchies using FIFOs to create safe channels for transferring asynchronous data.
  • How to implement hierarchies with different clocks.


This lab has three primary parts:

  • In Step 1, you will learn how to create hierarchies between the clock domains.
  • In Step 2, you will learn how to add FIFOs between the hierarchies.
  • In Step 3, you will learn how to add separate clock domains for each hierarchy.