The functional block diagram of the core is shown in the following figure.
Figure 1.
HBM/DDR BCAM Block Diagram
The above figure contains the following sub-blocks:
- CAM Database
- Match logic, registers and AXI3-Full Masters for
HBM memory access.
- AXI3-Full Master
- Protocol handling for memory transfers towards the HBM stacks via the AXI3 Switch. One or multiple AXI3-Full Masters depending on the lookup rate and the table size. Each AXI3-Full Master has a point-to-point connection to a PC via the AXI3 Switch. See the AXI High Bandwidth Controller LogiCORE IP Product Guide (PG276) for further information.
- 2 x HBM Stacks
-
HBM Stacks containing DRAM banks. The HBM/DDR BCAM can use one or two HBM stacks. The DRAM
banks are distributed and accessed through PCs.
- PC 0-PC 31
- Pseudo Channel 0 (PC 0) to PC 31. Each HBM stack supports 16 PCs.
- AXI4-Stream Master
- Protocol handling for the Lookup Responses.
- AXI4-Stream Slave
- Protocol handling for the Lookup Requests
- Lookup Request FIFO
- Transfers Lookup Requests from the Lookup Frequency domain to the Core Frequency domain.
- Lookup Response FIFO
- Transfers Lookup Responses from the Core Frequency domain to the Lookup Frequency domain.
- Management Request FIFO
- Buffering queue for Management Requests.
- Management Response FIFO
- Buffering queue for Management Responses.
- Strict Priority Scheduler
- Schedules lookup and Management Requests.
- AXI4-Lite Slave
- Protocol handling for accepting read/write requests and generating responses. The AXI4-Lite interface uses 12 bits of address and 32 bits of data.
The following clock domains are depicted in the block diagram:
- Lookup Frequency
- The clock frequency of the Lookup Request/Response interfaces (AXI4-Stream Slave/Master).
- Core Frequency
- The frequency of the CAM Database.
- AXI4-Lite Frequency
- The clock frequency of the AXI4-Lite bus.