- Associative array containing arbitrary (key, response) entries.
- Exact match key lookup returns hit/miss result and associated response value on hit.
- High throughput: 150 MLookups/s per HBM/DDR BCAM instance.
- Flexible: Supports a wide range of key widths, response widths, and lookup rates.
- Supports all key widths up to 992 bits and all response widths up to 1013 bits.
- Scalable: Supports one or multiple HBM/DDR BCAM instances, a single instance can use all DRAM within two HBM stacks allowing very large HBM/DDR BCAMs.
- High storage efficiency: 90% of the DRAM bits are transformed to CAM bits.
- Supports Error Correction Coding (ECC) by means of HBM configuration.
- Supports entry insert, delete, and update using highly portable software APIs.
- Can only be inferred from within P4 code using the Xilinx Vitis™ (VitisNetP4) tool.