The core requires correct parameters definition. This section contains information about constraining the core in the Vivado® Design Suite.
Required Constraints
The core requires correct clock definition constraints.
All clocks are completely asynchronous to each other. Required frequencies are given in the Clocking section.
Core Placement
In cases where the device used has more than one SLR, it is recommended to place the Core inside SLR0. While there is no restriction on placing the core in any other SLR, special care must be taken on AXI3 bus signals that would need to cross to SLR0, in order to connect to HBM.