“GT Selection and Configuration”选项卡支持您配置核的串行收发器功能。
图 1. “GT Selection and Configuration”选项卡 (Versal)
图 2. “GT Selection and Configuration”选项卡 (UltraScale/UltraScale+)
| 选项 | 值 | 默认 |
|---|---|---|
| GT Location | ||
| 选择将 GT IP 包含在核中还是包含在设计示例中 |
Include GT subcore in core Include GT subcore in example design |
Include GT subcore in core |
| GT Clocks 2 | ||
| GT RefClk (MHz) 1 |
161.1328125 195.3125 156.25 201.4160156 257.8125 322.265625 312.5 103.125 128.90625 206.25 309.375 |
161.1328125 |
| GT DRP Clock (MHz) | 10 - 250 MHz | 100.00 |
| Core to GT Association | ||
| GT 类型 |
GTY GTH GTM GTYP |
GTY |
| GT Selection |
基于器件/封装四通道组的选项。 例如： Quad X0Y1 Quad X0Y2 Quad X0Y3 ... |
Quad X0Y1 |
| Lane-00 到 Lane-03 |
根据器件/封装自动填充。 例如，如果 Num of Core = 4 且 GT Selection = Quad X0Y1，则 4 条通道分别为： X0Y4 X0Y5 X0Y6 X0Y7 |
|
| RX Equalization Mode |
Auto LPM DFE |
Auto |
| RX Insertion Loss at Nyquist (dB) | 取决于 GT Wizard | 30 |
| 其他 | ||
| Enable Pipeline Registers | 勾选或不勾选 | 不勾选 |
| Enable GT Interface for Board Based Design 3 | 勾选或不勾选 | 不勾选 |
| Enable Additional GT Control/Status and DRP Ports | 勾选或不勾选 | 不勾选 |
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