Reference Design - Reference Design

Download the reference design files for this application note from the Xilinx website.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter	Description
General
Developer name	Matt Ruan, Hanson He, Allan Zong
Target devices	Versal AI Core
Source code provided?	Yes
Source code format (if provided)	MATLAB script, AI Engine C code, Verilog, and Makefile
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list.	No
Simulation
Functional simulation performed	Yes
Timing simulation performed?	No
Test bench provided for functional and timing simulation?	No
Test bench format	Verilog and C
Simulator software and version	AI Engine Simulator and XSIM in Vitis 2021.2
SPICE/IBIS simulations	No
Static timing analysis performed?	Yes
Hardware Verification
Hardware verified?	Yes
Platform used for verification	VCK190