Heterogeneous System Design Methodology

Arbitrary Resampling Filter Design (XAPP1373)

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The design methodology described in Versal ACAP System and Solution Planning Methodology Guide (UG1504) enables various engineering teams to work on the same design in parallel. The Vitis software abstracts the functional blocks as black boxes, namely kernels, whose interfaces are no more than several AXI buses. Using the bit-true model programmed in MATLAB® or C language, you can precisely determine the behaviors of all the kernels and store the expected data on the AXI buses into text files. This approach effectively decouples the development of AI Engine and RTL.
Figure 1. Heterogeneous Design Development Flow

From the perspective of AI Engine developers, the whole PL design is reduced to a few input and output AXI streams with the clock frequencies and bus bit widths specified in the AI Engine test bench. Using this information, the AI Engine Simulator drives the input and saves the output accordingly. The AI Engine output data must bit-true match the reference test vectors, and the timestamps saved along with the data give an estimate of the throughput. It is highly recommended to have the AI Engine design fully validated in the AI Engine only simulation environment before integrating into larger systems.

Similarly, from the RTL engineers’ point of view, AI Engine kernels are modeled as AXI buses driven or monitored by the RTL test bench. The following figure shows one example of a pure RTL verification environment where two RTL kernels are under test. Many corner cases and extreme conditions are difficult to create with actual AI Engine kernels, and a pure RTL environment is useful to improve the robustness of the RTL design under special circumstances. Also, the simulation of pure RTL is much faster than AI Engine+PL+processing system (PS) co-simulation, leading to shorter turnaround time at the initial stage of development.

Figure 2. RTL Test Environment

After AI Engine and RTL kernels are independently developed, all the components can be packaged as kernels with only AXI buses for input and output. The Xilinx Vitis compiler is such a productive tool for integration that it only needs the declaration of kernels and a description about the sources and destinations of every AXI bus to automate the connection.

The AI Engine+PL+PS co-simulation should be performed on the integrated design, and the waveform view makes the debug process familiar to traditional RTL engineers. The C program running on the processor controls the test flow, reads back the test results collected by PL kernels, and prints the results via a COM port. During hardware test where the signal waveforms are not available, the printed information becomes the most convenient way to confirm that the design is working correctly.