Host Programming of QSPI Flash Host Programming of QSPI Flash (XAPP1372)

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1.1 English

Versal® devices have a built-in hardware QSPI controller in the platform management controller (PMC). The QSPI controller is routed to the PMC MIO pins when connected to QSPI flash—this is commonly used as a boot device. The QSPI controller can be accessed by both the internal processing system (PS) and an external CPU. This application note provides a reference design for using an external CPU programming QSPI flash. The external CPU, later known as the host, communicates with the QSPI controller in the Versal device through the PCIe® bus, network on chip (NoC), and PMC in a sequential manner. The PS is not involved in this entire process. For customers with limited memory resources, this application does not require DDR memory. The programmable logic (PL) block RAM is sufficient.

Download the reference design files for this application note from the Xilinx website. For detailed information about the design files, see Reference Design.