Host Software Design

Host Programming of QSPI Flash Host Programming of QSPI Flash (XAPP1372)

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1.1 English

Address Mapping

After setting up the host and VCK190 environment, list all the PCIe BAR spaces using the lspci command on the host computer. There are four PCIe BARs that the host could access, as shown in the following figure.

Figure 1. PCIe BARs

The BAR3 space has a size of 256 MB, which is from address 0xE000_0000 to 0xEFFF_FFFF. This BAR3 space is mapped to Versal device address 0x1_0000_0000 to 0x1_0FFFF_FFFF, which includes the PMC slave space. The QSPI controller is located at the PMC.

In this application note, the host also accesses the BAR4 space. There is a block RAM segment with a base address of 0xF000_0000 and size of 8 KB.

Table 1. PCIe BARs Address Mapping
PCIe BAR3 Space Device Name Versal Device Address Base
0xE103_0000 ~ 0xE103_FFFF QSPI controller 0x1_0103_0000 ~ 0x1_0103_FFFF (64 KB)
0xF000_0000 ~ 0xF000_1FFF

Block RAM Port0

For read operation
0xF000_0000 ~ 0xF000_1FFF (8 KB)

This block RAM has independent addresses for the two ports. As described previously, one address is for the host readback which maps to PCIe BAR4. Another address is written by the QSPI controller, so the software tells the QSPI controller that the BOARD_BRAM_BASE address is 0x201_8000_0000. This access is internal to the Versal device.

Table 2. Dual Ports Block RAM Address Mapping
PCIe BAR4 Device Name Size (B) Versal Device Address Base Host Access

Block RAM Port0

For read
8K 0xF000_000 Host accesses BAR space

Block RAM Port1

For write
8K 0x201_8000_0000 Host configures this 64-bit address to QSPI controller DMA address register

In the software application, the BOARD_BRAM_BASE and BOARD_BRAM_SIZE macros are defined in the file xqspipsu.h.

Figure 2. Address Mapping of Host Software

Host Application Data Flow

The following figure shows the overall programming guideline. Generally, the complete programming flow includes these subflows: QSPI Abort and Initialization, Read Flash ID, Erase Flash, Write Flash, and Verify Flash. In the Verify Flash subflow, there is a DMA Read Flash to the block RAM followed by a Host Read Block RAM to the Host local RAM and then a comparison on the host side.

Figure 3. Host Application Data Flow