Download the reference design files for this application note from the Xilinx website. The table below displays the reference design matrix.
Table 1:
|
Parameter |
Description |
|---|---|
|
General |
|
|
Developer Name(s) |
Jim Wesselkamper, Nathan Menhorn, Krzysztof Kepa |
|
Target Devices |
Zynq UltraScale+ devices |
|
Source code provided? |
Yes |
|
Source code format (if provided) |
C |
|
Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. |
|
|
Simulation |
|
|
Functional simulation performed |
No |
|
Timing simulation performed? |
No |
|
Testbench provided for functional and timing simulation? |
No |
|
Testbench format |
N/A |
|
Simulator software and version |
N/A |
|
SPICE/IBIS simulations |
N/A |
|
Implementation software tool(s) and version |
Vitis 2021.2 |
|
Static timing analysis performed? |
No |
|
Hardware Verification |
|
|
Hardware verified? |
Yes |
|
Platform used for verification |
ZCU102 evaluation board |
Reference Design Checklist