Creating the Zynq UltraScale+ ZCU102 Evaluation Board Hardware Design

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1. Open Vivado Design Suite .

2. In the Quick Start tab click Create Project .

3. Click Next in the Create a New Vivado Project page.

4. Enter ZCU102 in the Project name.

5. Enter or select an appropriate working directory in the Project location.

6. Click Next on the Project Name page.

7. In Project Type , select RTL Project and uncheck two boxes for Do not specify sources at this time and Project is an extensible Vitis platform .

8. Click Next on the Project Type page.

9. Click Next on the Add Sources page.

10. Click Next on the Add Constraints (optional) page.

11. On the Default Part page, click the Boards tab.

12. Type in ZCU102 in the Search.

13. Click the Zynq UltraScale+ ZCU102 Evaluation Board .

14. Click Next on the Default Part page.

15. Click Finish on the New Project Summary Page and wait while the project is being created.

16. In the Project Manager tab located on the left of the Vivado workspace, click IP INTEGRATOR > Create Block Design .

17. When the Create Block Design window appears, type in ZCU102 in Design name . Leave everything else set to default.

18. Click OK and wait while the design is created.

19. In the Diagram section of the workspace, located on the top right, click the + button to add IP.

20. When the Search box appears, type in ZYNQ .

21. Double-click Zynq UltraScale+ MPSoC and wait while the part is added to the design.

22. Click Run Block Automation at the top of the Diagram window.

23. After the Run Block Automation window appears, select All Automation and Apply Board Preset , click OK and wait while the automation takes place.

24. Double-click the Zynq UltraScale+ part in the Diagram window.

25. Click Page Navigator > PS-PL Configuration located on the left of the Zynq UltraScale+ (3.3) window.

26. Click PS-PL Interfaces located in the PS-PL Configuration window.

27. Click Master Interface and uncheck the AXI HPM0 FPD and AXI HPM1 FPD parameters.

28. Click OK to close the window.

29. Pres F6 to validate the design.

30. Click OK when the Validate Design window opens indicating the validation was successful.

31. In the BLOCK DESIGN window, click the Sources tab in the upper left-hand corner.

32. Right-click ZCU102 under Design Sources and select Create HDL Wrapper .

33. When the Create HDL Wrapper window opens, click Let Vivado manage wrapper and auto-update , then click OK and wait while the sources are created.

34. In the BLOCK DESIGN window in the upper left corner on the Sources tab, expand the ZCU102_wrapper.

35. Right-click ZCU102_i: ZCU102 and select Generate Output Products .

36. Leave the default settings in the Generate Output Products window. Click Generate and wait while the IP is being generated.

37. Click OK when the Generate Output Products window displays Out-of-context module run was launched for generating output products .