Step 6: Clock Interaction Report - 2024.1 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

Document ID
UG945
Release Date
2024-06-12
Version
2024.1 English

After or during constraints creation, you must verify that the constraints are complete and safe. Vivado Design Suite times all clocks together by default unless you specify otherwise by defining clock groups or other timing exceptions. The set_clock_groups command specifies asynchronous or exclusive clock domains and disables timing analysis between them. You can also use the set_false_path exception between two clocks to disable timing on all paths between them, or use it on specific netlist objects to only disable some paths. The set_multicycle_path exception modifies the clock edges used during timing analysis instead of the default single cycle assumption. For more information on using these constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903). For more information on Clock Interaction, click here.

Vivado automatically infers timing path requirements for paths that cross between two different clock domains, called inter-clock paths, making assumptions regarding phase and offset. The Report Clock Interaction command reports inter-clock paths, to help identify potential problems such as unrealistic setup or hold requirements between two clocks, or unsafe timing between asynchronous clocks (no known phase relationship) that can lead to unstable hardware behavior. For more information on the Clock Interaction Report, see Details of the Clock Interaction Report in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

  1. From the Flow Navigator, select Synthesized Design > Report Clock Interaction and click OK in the Report Clock Interaction dialog box to accept the default settings.

    The Vivado IDE generates a graphical matrix illustrating the relationship of the various clocks in the design, as shown in the previous figure. For this design, the primary clock (sysClk) connects to an MMCM, which generates six additional clocks. The clock interactions shown are between these generated clocks. In addition, the Timing Constraints wizard created additional generated clocks and virtual clocks to fully constrain the design.

    In general, the Clock Interaction report shows clock pairs with no path between them (black), with paths safely timed (green and light blue), with paths not safely timed (red and orange) and with paths covered by Max Delay Datapath Only constraints. In this design, only black cells and green cells are displayed in the matrix.

    Important: Green in the matrix does not mean that timing is met, it simply means that the timing constraints and the clock tree topologies allows safe timing analysis and accurate slack computation.

    In the Clock Interaction report, unsafe means there is no common primary clock (no known phase relationship), or no common node (uncommon scenario that results in unknown phase relationship), or no common clock period within the first 1000 clock cycles of the source and destination clocks. The Vivado timing engine selects edges on the launch and capture clocks based on the first 1000 cycles, but these edges might not reflect the most pessimistic analysis between the clocks.

    Tip: The colors described here are the default colors. Your colors might be configured differently from those shown in the previous figure.
  2. Close the Clock Interaction window by clicking the Close button in the window tab.