IP Facts - 1.0 English

Utility Flip-Flop LogiCORE IP Product Guide (PG413)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal® ACAP, Virtex® UltraScale+™ , Kintex® UltraScale+™ , Artix UltraScale+, Zynq® UltraScale+™ MPSoC
Supported User Interfaces N/A
Resources N/A
Provided with Core
Design Files Verilog
Example Design Not Provided
Test Bench Not Provided
Constraints File None
Simulation Model Verilog
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.