This core runs on a single clock input port to register the probe values. For best results, it should be the same clock signal that is synchronous to the design logic that is attached to the probe parts of the Utility Flip-Flop IP core.
This core runs on a single clock input port to register the probe values. For best results, it should be the same clock signal that is synchronous to the design logic that is attached to the probe parts of the Utility Flip-Flop IP core.