M**_AXI Interface Ports - 2.0 English

AI Engine LogiCORE IP Product Guide (PG358)
Document ID
PG358
Release Date
2021-07-02
Version
2.0 English

The following table shows the M**_AXI Interface Ports and their descriptions.

Table 1. M**_AXI Interface Ports
Port Name I/O Description
m**_axi_awaddr (C_M**_AXI_ADDR_WIDTH – 1: 0) O Write Address Channel Address Bus
m**_axi_awid

(C_M**_AXI_ID_WIDTH – 1: 0)

O Write Address Channel ID
m**_axi_awuser (C_M**_AXI_AWUSER_WIDTH – 1: 0) O Write Address Channel user
m**_axi_awlen[7:0] O Write Address Channel Burst Length. In data beats – 1.
m**_axi_awsize[2: 0] O Write Address Channel Burst Size. Indicates width of burst transfer.
  • 000b = 1-byte (8-bit wide burst)
  • 001b = 2 bytes (16-bit wide burst)
  • 010b = 4 bytes (32-bit wide burst)
  • 011b = 8 bytes (64-bit wide burst)
  • 100b = 16 bytes (128-bit wide burst)
  • 101b = 32 bytes (256-bit wide burst)
  • 110b = 64 bytes (512-bit wide burst)
  • 111b = 128 bytes (1,024-bit wide burst)
m**_axi_awburst[1:0] O Write Address Channel Burst Type. Indicates type burst.
  • 00b = FIXED – Fixed address
  • 01b = INCR – Incrementing address
  • 10b = WRAP – Not supported
  • 11b = Reserved
m**_axi_awprot[2:0] O Write Address Channel Protection. This is always driven with a constant output of 0010b.
m**_axi_awlock O Write Address Channel exclusive access.
m**_axi_awqos[3:0] O Write Address Channel QoS
m**_axi_awregion[3:0] O Write Address Channel Region
m**_axi_awcache[3:0] O Write Address Channel Cache
m**_axi_awvalid O Write Address Channel Write Address Valid. Indicates if m**_axi_awaddr is valid.
  • 0 = write address is not valid
  • 1 = write address is valid
m**_axi_awready O Write Address Channel Write Address Ready. Indicates target is ready to accept the write address.
  • 0 = target not ready to accept address
  • 1 = target ready to accept address
m**_axi_wdata (C_M**_AXI_DATA_WIDTH – 1:0) O Write Data Channel Write Data Bus
m**_axi_wstrb (C_M**_AXI_DATA_WIDTH/ 8 – 1:0) O Write Data Channel Write Strobe Bus. Indicates which bytes are valid in the write data bus. This value is passed from the stream side strobe bus.
m**_axi_wuser (C_M**_AXI_WUSER_WIDTH – 1: 0) O Write Data Channel user
m**_axi_wlast O Write Data Channel Last. Indicates the last data beat of a burst transfer.
  • 0 = Not last data beat
  • 1 = Last data beat
m**_axi_wvalid O Write Data Channel Data Valid. Indicates m**_axi_wdata is valid.
  • 0 = Not valid write data
  • 1 = Valid write data
m**_axi_wready I Write Data Channel Ready. Indicates the write channel target is ready to accept write data.
  • 0 = target is not ready
  • 1 = target is ready
m**_axi_bresp[1:0] I Write Response Channel Response. Indicates results of the write transfer.
  • 00b = OKAY – Normal access has been successful
  • 01b = EXOKAY – Not supported
  • 10b = SLVERR – Slave returned error on transfer
  • 11b = DECERR – Decode error, transfer targeted unmapped address
m**_axi_bvalid I Write Response Channel Response Valid. Indicates response, m**_axi_bresp, is valid.
  • 0 = Response is not valid
  • 1 = Response is valid
m**_axi_bid

(C_M**_AXI_ID_WIDTH – 1: 0)

 I Write Response Channel ID
m**_axi_buser

(C_M**_AXI_BUSER_WIDTH – 1: 0)

I Write Response Channel user
m**_axi_bready O Write Response Channel Ready. Indicates write channel is ready to receive response.
  • 0 = Not ready to receive response
  • 1 = Ready to receive response
m**_axi_araddr (C_M**_AXI_ADDR_WIDTH – 1:0) O Read Address Channel Address Bus
m**_axi_arid

(C_M**_AXI_ID_WIDTH – 1: 0)

 O Read Address Channel ID
m**_axi_aruser

(C_M**_AXI_ARUSER_WIDTH – 1: 0)

 O Read Address Channel user
m**_axi_arlen[7:0] O Read Address Channel Burst Length. In data beats – 1.
m**_axi_arsize[2:0] O Read Address Channel Burst Size. Indicates width of burst transfer.
  • 000b = 1-byte (8-bit wide burst)
  • 001b = 2 bytes (16-bit wide burst)
  • 010b = 4 bytes (32-bit wide burst)
  • 011b = 8 bytes (64-bit wide burst)
  • 100b = 16 bytes (128-bit wide burst)
  • 101b = 32 bytes (256-bit wide burst)
  • 110b = 64 bytes (512-bit wide burst)
  • 111b = 128 bytes (1,024-bit wide burst)
m**_axi_arburst[1:0] O Read Address Channel Burst Type. Indicates type burst.
  • 00b = FIXED – Fixed address
  • 01b = INCR – Incrementing address
  • 10b = WRAP – Not supported
  • 11b = Reserved
m**_axi_arprot[2:0] O Read Address Channel Protection. This is always driven with a constant output of 0010b.
m**_axi_arcache[3:0] O Read Address Channel Cache
m**_axi_arlock O Read Address Channel exclusive access.
m**_axi_arqos[3:0] O Read Address Channel QoS
m**_axi_arregion[3:0] O Read Address Channel Region
m**_axi_arvalid O Read Address Channel Read Address Valid. Indicates if m**_axi_araddr is valid. 0 = write address is not valid 1 = write address is valid
m**_axi_arready I Read Address Channel Read Address Ready. Indicates target is ready to accept the read address.
  • 0 = Target not ready to accept address
  • 1 = Target ready to accept address
m**_axi_rdata (C_M**_AXI_DATA_WIDTH – 1:0) I Read Data Channel Read Data Bus
m**_axi_rid

(C_M**_AXI_ID_WIDTH – 1: 0)

I Read Data Channel ID
m**_axi_ruser (C_M**_AXI_RUSER_WIDTH – 1: 0) I Read Data Channel user
m**_axi_rlast I Read Data Channel Last. Indicates the last data beat of a burst transfer.
  • 0 = Not last data beat
  • 1 = Last data beat
m**_axi_rvalid I Read Data Channel Data Valid. Indicates m**_axi_rdata is valid.
  • 0 = Not valid write data
  • 1 = Valid write data
m**_axi_rready O Read Data Channel Ready.
  • 0 = Target is not ready
  • 1 = Target is ready
m**_axi_rresp[1:0] I Read Response Channel Response. Indicates results of the write transfer.
  • 00b = OKAY – Normal access has been successful
  • 01b = EXOKAY – Not supported
  • 10b = SLVERR – Slave returned error on transfer
  • 11b = DECERR – Decode error, transfer targeted unmapped address