Core Specifics |
Supported Device Family
1
|
Versal™
ACAP AI
Core |
Supported User Interfaces |
AXI4, AXI4-Stream
|
Resources |
N/A |
Provided with Core
|
Design Files |
Register Transfer Level (RTL) |
Example Design |
Not Provided |
Test Bench |
Not Provided |
Constraints File |
Not Provided |
Simulation Model |
Not Provided |
Supported S/W Driver |
N/A |
Tested Design Flows
2
|
Design Entry |
Vivado® Design Suite
|
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 75675
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the
Vivado®
IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|