The following table shows the clock parameters and their descriptions.
| Clock | Description |
|---|---|
| aclk* | These clock ports are associated with AI Engine IP to PL AXI4-Stream and PL to AI Engine AXI4-Stream interfaces. One or more interfaces can be associated with one of these clock ports. |
| s**_axi_aclk | These clock ports are associated with S**_AXI interfaces. These are meant to be connected to a NoC IP only. Each interface is associated with one dedicated clock port and should not be used for any other purpose. |
| m**_axi_aclk | These clock ports are associated with S**_AXI interfaces. These are meant to be connected to a NoC IP only. Each interface is associated with one dedicated clock port and should not be used for any other purpose. |
| noc_aclk* | These clock ports are associated with AI Engine to NoC AXI4-Stream and NoC to AI Engine AXI4-Stream interfaces. These are meant to be connected to a NoC IP only. Each interface is associated with one dedicated clock port and should not be used for any other purpose. |
| trig_in_*_clk | Trigger in clock. |
| trig_out_*_clk | Trigger out clock. |