REG0 Register (0x2000+CODE*0x10) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)
Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. REG0 Register
Bit Access Type Description
30:16 R/W

K: Number of information bits.

2 ≤ K ≤ 32766, multiples of P. Also K ≤ 256 × P.
15:0 R/W

N: Number of codeword bits.

4 ≤ N ≤ 32768 multiples of P. Also N ≤ 256 × P and N>K.

  1. See Non-5G Control Interface Definition for LDPC Decode and Encode for CODE definition.
  2. Setting invalid parameter values results in an interrupt and otherwise undefined behavior, requiring a reset to recover.
  3. The default value is undefined.
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