Non-5G NR Control Interface Definition for LDPC Decode - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

When the supported standard is not 5G NR the control data interface is 32 bits with the fields shown in the following table for LDPC decode.

Table 1. Non-5G NR Control Interface Definition for LDPC Decode
Field Bits Range Description
id 31:24 0 to 255 External block identifier to be passed through to status output
max_iterations 23:18 1 to 63 Maximum number of iterations
term_on_no_change 17 0 or 1

0: Do not terminate early if there is no change in hard bits for the whole block (information and parity) between iterations

1: Terminate early if there is no change in hard bits for the whole block (information and parity) between iterations

term_on_pass 16 0 or 1

0: Do not terminate early on passing parity check

1: Terminate early on passing parity check

include_parity_op 15 0 to 1

0: Output systematic values only

1: Output systematic values and parity

hard_op 14 0 to 1

0: Soft output

1: Hard output

- 13:7 - Reserved
code 6:0 0 to 127 Code number (CODE) used to specify which set of LDPC code parameters are to be used on the block