AXI4-Stream Interface - 1.1 English

Basic Handshake

The following figure shows the transfer of data in an AXI4-Stream channel. The tvalid signal is driven by the source (master) side of the channel and tready is driven by the destination (slave) side. The tvalid signal indicates that the values in the payload fields (tdata and tlast) are valid. The tready signal indicates that the slave is ready to accept data. When both tvalid and tready are asserted in the same clock cycle, a transfer occurs.

The order of tvalid or tready going High or Low is not important; data is only transferred when both tvalid and tready are High.

Figure 1. Data Transfer in an AXI4-Stream Channel

Use of TLAST

The core always produces tlast signals on all output channels; however the sizes of input packets are always either fixed or given explicitly using associated control information. Hence the tlast on input channels is actually redundant; requiring a source to provide a suitable tlast could hinder interoperability. Therefore the core has been specifically designed to ignore tlast inputs for packet delineation and use internal knowledge of packet size instead. In all such cases, the core also produces two event signals, one to indicate tlast was unexpectedly asserted (tlast unexpected events) and one to indicate tlast was unexpectedly deasserted (tlast missing events). In all situations the core continues to operate as if tlast was correctly applied, and the events can be interpreted as required. For further details of tlast handling in Xilinx® IP see the Vivado Design Suite: AXI Reference Guide (UG1037).