DCI—VRP Termination

The K26 SOM is designed for compute demanding applications. It leverages the AMD Zynq™ UltraScale+™ MPSoCs and incorporates the compute-capable XCK26-SFVC784-2LV. Zynq UltraScale+ MPSoCs incorporate digitally controlled impedance (DCI) technology. This allows product development to reduce PCB size through internally controlling the impedance of I/O pins, removing the need for external termination resistors. DCI configuration is only used on HP I/O banks within the MPSoCs.

For more information on DCI, see the UltraScale Architecture SelectIO Resources User Guide (UG571), with specific attention to the DCI—Only Available in the HP I/O Banks and VRP External Resistance Design Migration Guidelines topics. The K26 has three HP I/O banks. When designing with the SOMs, the following table defines the VRP configuration for each bank. The value of 240Ω was chosen based upon the previous references.