FPGA Resource Information

Alveo U280 Data Center Accelerator Card Data Sheet (DS963)

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1.7 English

The AMD Alveo U280 accelerator card is a custom-built UltraScale+ FPGA that runs optimally (and exclusively) on the Alveo architecture. The Alveo U280 card features the XCU280 FPGA, which uses AMD stacked silicon interconnect (SSI) technology to deliver breakthrough FPGA capacity, bandwidth, and power efficiency. This technology allows for increased density by combining multiple super logic regions (SLRs). The XCU280 comprises three SLRs with the bottom SLR (SLR0) integrating an HBM controller to interface with the adjacent 8 GB HBM2 memory. The bottom SLR also connects to 16 lanes of PCI Express® that can operate up to 16 GT/s (Gen4). SLR0 and SLR1 both connect to a DDR4 16 GB, 2400 MT/s, 64-bit with error correcting code (ECC) DIMM for a total of 32 GB of DDR4. SLR2 connects two QSFP28 connectors with associated clocks generated on the U280 board. The following figure shows the three SLR regions along with the connections for PCIe, DDR4, and QSFP28. The HBM is co-located on the XCU280 device and connects directly to SLR0.

Figure 1. Floorplan of the XCU280 Device

For customers using the AMD Vitis™ application acceleration development flow, a platform is created that manages the PCIe interface, data transfers, and card status information. It also remotely loads kernels and performs several functions that greatly simplify developing an application. This platform is part of the static region (an area of the FPGA that is not reconfigurable). This platform consumes resources from the available resources listed in Table 1. The specific amount of resources depends on which platform, and even which version of a platform is used. This information is available in Alveo Data Center Accelerator Card Platforms User Guide (UG1120).

For developing applications, refer to the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).