Power Supply Requirements

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID

DS931

Release Date

2024-05-30

Revision

1.7 English

Table 1 shows the minimum current, in addition to I_CCQ maximum, required by each Artix UltraScale+ FPGA for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after V_CCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate current drain on these supplies. XPE is also used to estimate power-on current for all supplies.

Table 1. Power-on Current by Device
Device	I_CCINTMIN	I_CCBRAMMIN + I_{CCINT_IOMIN}	I_CCOMIN	I_CCAUXMIN + I_{CCAUX_IOMIN}	Units
XCAU7P XAAU7P	I_CCINTQ + 770	I_CCBRAMQ + I_{CCINT_IOQ} + 409	I_CCOQ + 50	I_CCAUXQ + I_{CCAUX_IOQ} + 386	mA
XCAU10P XAAU10P	I_CCINTQ + 770	I_CCBRAMQ + I_{CCINT_IOQ} + 409	I_CCOQ + 50	I_CCAUXQ + I_{CCAUX_IOQ} + 386	mA
XCAU15P XAAU15P	I_CCINTQ + 770	I_CCBRAMQ + I_{CCINT_IOQ} + 409	I_CCOQ + 50	I_CCAUXQ + I_{CCAUX_IOQ} + 386	mA
XCAU20P	I_CCINTQ + 770	I_CCBRAMQ + I_{CCINT_IOQ} + 476	I_CCOQ + 50	I_CCAUXQ + I_{CCAUX_IOQ} + 515	mA
XCAU25P	I_CCINTQ + 770	I_CCBRAMQ + I_{CCINT_IOQ} + 476	I_CCOQ + 50	I_CCAUXQ + I_{CCAUX_IOQ} + 515	mA

Table 2. Power Supply Ramp Time
Symbol	Description	Min	Max	Units
T_VCCINT	Ramp time from GND to 95% of V_CCINT	0.2	40	ms
T_{VCCINT_IO}	Ramp time from GND to 95% of V_{CCINT_IO}	0.2	40	ms
T_VCCO	Ramp time from GND to 95% of V_CCO	0.2	40	ms
T_VCCAUX	Ramp time from GND to 95% of V_CCAUX	0.2	40	ms
T_VCCBRAM	Ramp time from GND to 95% of V_CCBRAM	0.2	40	ms
T_MGTAVCC	Ramp time from GND to 95% of V_MGTAVCC	0.2	40	ms
T_MGTAVTT	Ramp time from GND to 95% of V_MGTAVTT	0.2	40	ms
T_MGTVCCAUX	Ramp time from GND to 95% of V_MGTVCCAUX	0.2	40	ms