Device Pin-to-Pin Input Parameter Guidelines

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)
Document ID
DS931
Release Date
2024-05-30
Revision
1.7 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSFD_AU7P Global clock input and input flip-flop (or latch) without MMCM Setup XCAU7P 2.21 2.27 3.75 ns
TPHFD_AU7P Hold –0.30 –0.30 –0.96 ns
TPSFD_AU10P Setup XCAU10P 2.07 2.14 3.50 ns
TPHFD_AU10P Hold –0.23 –0.23 –0.87 ns
TPSFD_AU15P Setup XCAU15P 2.07 2.14 3.50 ns
TPHFD_AU15P Hold –0.23 –0.23 –0.87 ns
TPSFD_AU20P Setup XCAU20P 2.28 2.38 3.83 ns
TPHFD_AU20P Hold –0.36 –0.36 –1.04 ns
TPSFD_AU25P Setup XCAU25P 2.28 2.38 3.83 ns
TPHFD_AU25P Hold –0.36 –0.36 –1.04 ns
TPSFD_XAAU7P Setup XAAU7P N/A 2.27 3.75 ns
TPHFD_XAAU7P Hold N/A –0.30 –0.96 ns
TPSFD_XAAU10P Setup XAAU10P N/A 2.14 N/A ns
TPHFD_XAAU10P Hold N/A –0.23 N/A ns
TPSFD_XAAU15P Setup XAAU15P N/A 2.14 N/A ns
TPHFD_XAAU15P Hold N/A –0.23 N/A ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 2. Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSMMCMCC_AU7P Global clock input and input flip-flop (or latch) with MMCM Setup XCAU7P 1.30 1.37 1.37 ns
TPHMMCMCC_AU7P Hold –0.17 –0.17 –0.14 ns
TPSMMCMCC_AU10P Setup XCAU10P 1.82 1.95 1.95 ns
TPHMMCMCC_AU10P Hold –0.21 –0.21 –0.26 ns
TPSMMCMCC_AU15P Setup XCAU15P 1.82 1.95 1.95 ns
TPHMMCMCC_AU15P Hold –0.21 –0.21 –0.26 ns
TPSMMCMCC_AU20P Setup XCAU20P 2.04 2.16 2.16 ns
TPHMMCMCC_AU20P Hold –0.17 –0.17 –0.23 ns
TPSMMCMCC_AU25P Setup XCAU25P 2.04 2.16 2.16 ns
TPHMMCMCC_AU25P Hold –0.17 –0.17 –0.23 ns
TPSMMCMCC_XAAU7P Setup XAAU7P N/A 1.37 1.37 ns
TPHMMCMCC_XAAU7P Hold N/A –0.17 –0.14 ns
TPSMMCMCC_XAAU10P Setup XAAU10P N/A 1.95 N/A ns
TPHMMCMCC_XAAU10P Hold N/A –0.21 N/A ns
TPSMMCMCC_XAAU15P Setup XAAU15P N/A 1.95 N/A ns
TPHMMCMCC_XAAU15P Hold N/A –0.21 N/A ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 3. Sampling Window
Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
TSAMP_BUFG 1 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 125 150 ps
TSAMP_NATIVE_BISC 3 60 85 110 ps
  1. This parameter indicates the total sampling error of the Artix UltraScale+ FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
  2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
  3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).
Table 4. Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
TINPUT_LOGIC_UNCERTAINTY 1 40 ps
TCAL_ERROR 2 24 ps
  1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3).
  2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.