Product Details

T2 Telco Accelerator Card Data Sheet (DS1000)

Document ID
Release Date
1.0 English
Table 1. T2 Telco Accelerator Card Specifications
Specification T2 Telco Accelerator Card
Product SKU

TA-T2-P6G-PQ-EV (encryption enabled)

TA-T2-P6G-PQ-DV (encryption disabled)

PCIe® lanes

Gen3 x16

Gen4 x16 with bifurcation support (2x Gen4 x8)

Total thermal design power 55W
Estimated typical electrical design power (for expected performance) 51W
Estimated maximum electrical design power (for expected performance) 60W
Thermal cooling solution Passive
Weight 351 g
Onboard memory

Programmable logic (PL): 1x banks of 4 GB x72 (64-bit + 8-bit ECC)

Processing system (PS): 1x banks of 2 GB x 40 (32-bit + 8-bit ECC)

Total capacity 4 GB in PL in Zynq UltraScale+ RFSoC device

Total capacity 2 GB in PS in Zynq UltraScale+ RFSoC device

Form factor HHHL
SoC resources XCZU48DR-2FSVG1517E
Application processing unit (APU) 64-bit quad-core Arm® Cortex®-A53 MPCore up to 1.3 GHz
Real-time processing unit (RPU) Dual-core Arm® Cortex®-R5F MPCore up to 600 MHz
Network interfaces None
System logic cells 930,000
Lookup tables 425,000
DSP slices 4,272
Maximum distributed RAM (Mb) 13
UltraRAM (Mb) 22.5
Total block RAM (Mb) 38
Package FSVG1517 (40 x 40 mm)

The Zynq UltraScale+ RFSoC device is at the core of the T2 card architecture. See the Zynq UltraScale+ RFSoC Product Selection Guide for more details about this device.

Figure 1. T2 Card High-Level Block Diagram

PCIe Connector/Data Rates

The T2 card is compliant to the PCI Express Base Specification Revision 3.1 (registration required) supporting up to 16.0 GT/s (Gen4) data rates. The PCI Express finger supports 16 lanes (x16), but these 16 lanes can be bifurcated into two x8 PCIe interfaces for Gen4 x8 mode of operation.

DDR Memory Interface

The Zynq UltraScale+ RFSoC is interfaced with an external DDR4 chip for data buffering applications.
  • One memory controller can be implemented in the Zynq UltraScale+ RFSoC PL with a four-channel 64-bit DDR4 interface with ECC (PL). Each 64-bit channel can be populated with 4 GB of memory.
  • One memory controller can be implemented in the Zynq UltraScale+ RFSoC PS with a two-channel 32-bit DDR4 interface with ECC (PS). Each 32-bit channel can be populated with 2 GB of memory.
  • The DDR4 memory operating frequency is 1200 MHz/2400 MTPS.

Satellite Controller

A TI MSP432 satellite controller resides on the T2 card to control and monitor voltages, currents, and temperatures. The host server board management controller (BMC) can interact with the satellite controller to monitor and control the T2 card through out-of-band communication. Xilinx supports the PLDM protocol over MCTP over SMBUS, complying with DMTF standards.


Virtualization requires significant acceleration of latency-sensitive and compute-intensive functions. The T2 card performance metrics below are based on in-lab measurements of the card reference design.

The peak throughput and average latency of the card are given in the following table. The ZU48DR device has eight SD-FEC cores which can be configured as LDPC encoder/decoder or turbo decoder to achieve the desired throughput.

A combination of uplink (decode) or downlink (encode) can be flexibly implemented on the T2 card. The T2 card uses the PCIe performance of Gen3 x16 or Gen4 x8 (around 100 Gb/s) for lookaside 5G L1 acceleration.

Table 2. L1 LDPC Performance
Configuration Throughput per SD-FEC Core Average Latency
Encoder 33 Gb/s <10 μs
Decoder 12 Gb/s <10 μs