PS-PL Trace - 3.1 English

Control Interfaces and Processing System LogiCORE IP Product Guide

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3.1 English

You can generate Trace ATB signal to PL. AMBA Trace Bus interrupt is generated from this option, which is connected to CoreSight module. Coresight gets the debug information from different cores in PL and can feed the same to ILA/CIPS core.

Enabling PL to PS Advanced Trace Bus (ATB) ports will enable ATB ports on the CIPS IP that allows PL access to the advanced trace bus.

PL to PS System Trace Macrocell (STM) event port will enable the STM ports on the CIPS IP that allows PL access to the coresight System Trace Macrocell.

Off-Chip parallel trace allows to output trace data from the PS via MIO or EMIO to PL. The MIO bus is 16-bit wide at most, whereas the EMIO bus can be upto 32-bit wide. Enabling PL_TracePeripheral allows to then select MIO or EMIO from the IO panel view.

For trace via EMIO, a PL IP can be used to connect to the PS-PL trace interface and output to the PL XIOs the trace data according to the Arm Trace standard. The PL XIOs are topically connected to a Mictor connector where a trace probe can collect the trace data for analysis in a debugging IDE.

Figure 1. PS-PL Trace Configuration