Block Automation - 3.1 English

Control Interfaces and Processing System LogiCORE IP Product Guide

Document ID
PG352
Release Date
2021-10-27
Version
3.1 English

Vivado® supports the Block Automation for Control, Interfaces and Processing System IP to aid in integrating it into the larger design. After adding the CIPS IP to the block diagram, the block automation banner pops up. Click Run Block Automation to open the block automation page.

Figure 1. Block Automation
Block automation supports the following options:
Memory Controller
You can select x1/x2/x4 interleaved DDR4 or LPDDR DRAM controllers and a new/existing NoC to be connected to the CIPS IP core.
PL clocks/PL resets
You can select 0-4 PL clocks and 0-4 reset signals which are exposed to PL.
Design Flows
The two Design Flows are available and the selected flow is reflected in the CIPS IP.
Figure 2. Run Block Automation

When you click OK, a validate ready design is provided with input requirements.

Note: The block automation banner disappears when CIPS IP instance configuration is updated/changed. Thus, it must be the first configuration step if intended to be used.