You can set the USER_SLL_REG property on registers that you expect to
be placed at an SLR crossing boundary. The USER_SLL_REG constraint is ignored by
place_design if the register D and Q pins are
connected to a net that either does not cross an SLR boundary or drives loads placed
in multiple SLRs. For example:
set_property USER_SLL_REG TRUE [get_cells {reg_A reg_B}]