Using IBERT GTY and GTM for Transceiver Link Characterization - 2023.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2023-05-24
Version
2023.1 English

Versal device GTY and GTM transceivers support an Integrated Bit Error Ratio Tester (IBERT) which enables in-system serial I/O validation and debug. This allows the measuring and optimization of high-speed serial I/O links.

IBERT should be used when you are interested in measuring the quality of a signal after receiver equalization has been applied to the received signal.

Unlike previous architectures, the Versal device IBERT functionality is integrated into the GTY and GTM transceivers and requires only a design which uses the transceivers. For more information on IBERT functionality, see this link in the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).