Working with Sources in Non-Project Mode - 2022.2 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)
Document ID
UG895
Release Date
2022-11-09
Version
2022.2 English

Unlike Project Mode in which source files are managed for you, source files are under your control in Non-Project Mode. Using Tcl commands, you specify the files to process and output files to generate, including netlist, bitstream, and report files. Table 1 shows commonly used Project Mode commands and corresponding Non-Project Mode commands. For more information on Project Mode and Non-Project Mode, see this link in the Vivado Design Suite User Guide: Design Flows Overview (UG892). For more information on Tcl commands, see the Vivado Design Suite Tcl Command Reference Guide (UG835).

Note: In Non-Project Mode, files are compiled in the order the read_* commands are listed in the Tcl script.
Note: To Select a new part in the current installation, close the current project and upgrade the current installation to add additional part.
Table 1. Project Mode and Non-Project Mode Commands
Action Project Mode Command Non-Project Mode Command
Reading design sources

add_files

import_files

read_<file_type>

(for example: read_verilog, read_vhdl, read_xdc, read_edif, and read_ip)

You can import an NGC file in Non-Project Mode using the read_edif command.
Running synthesis launch_runs synth_1 synth_design
Running implementation launch_runs impl_1

opt_design

place_design

phys_opt_design

route_design

launch_runs impl_1 -to_step write_bitstream write_bitstream <file_name>
Generating reports

report_timing

report_timing_summary

report_drc

report_methodology

report_clock_interaction

report_utlization

report_route_status

In Project Mode, many reports are automatically generated. For a list of all reports, enter: help report_*.

 Same as Project Mode
Running simulation launch_xsim

xsim

This command launches Vivado simulation outside of the Vivado IDE.
Writing design checkpoints

write_checkpoint <file_name>.dcp

In Project Mode, DCP files are automatically created for each stage of implementation.

 Same as Project Mode

Following is an example of a Non-Project Mode script, which reads in various source files:

# create_bft_batch.tcl
# bft sample design 
# A Vivado script that demonstrates a very simple RTL-to-bitstream batch flow
#
# NOTE: typical usage would be "vivado -mode tcl -source create_bft_batch.tcl" 
#
# STEP#0: define output directory area.
#
set outputDir ./Tutorial_Created_Data/bft_output       
file mkdir $outputDir
#
# STEP#1: setup design sources and constraints
#
read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]     
read_vhdl ./Sources/hdl/bft.vhdl
read_verilog [ glob ./Sources/hdl/*.v ]
read_xdc ./Sources/bft_full.xdc
#
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint 
design
#
synth_design -top bft -part xc7k70tfbg484-2 -flatten rebuilt  
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
#
# STEP#3: run placement and logic optimzation, check against the UltraFast 
methodology checks, report utilization and timing estimates, write checkpoint design
#
opt_design
report_methodology -file $outputDir/post_opt_methodology.rpt
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
#
# STEP#4: run router, report actual utilization and timing, write checkpoint design, 
run drc, write verilog and xdc out
#
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file 
$outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
#
# STEP#5: generate a bitstream
# 
write_bitstream -force $outputDir/bft.bit