The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/09/2022 Version 2022.2 | |
| Working with Vitis HLS Sources | Changed all instances of Vivado HLS to Vitis HLS. |
| Working with Model Composer Sources | Changed Vivado HLS to Vitis HLS. |
| Steps to Use Board File Linter | Edited text in step 1 and code in step 5. |
| References | Changed reference for UG902 to UG1399. |
| 05/11/2022 Version 2022.1 | |
| Navigating Content by Design Process | Added new section. |
| Post-Synthesis Projects | Added an important note regarding ISE IP. |
| Imported Projects | Updated the section. |
| Importing an External Project | Updated the section. |
| Tcl Commands for Importing a Project | Updated the section. |
| Generating Output Products for IP Cores | Updated an image. |
| Generating Output Products for Block Designs | Updated an image. |
| Components | Updated the section. |
| IP Board Awareness | Added new section. |