Run C Synthesis - 2022.2 English

Vitis Tutorials: Getting Started (XD098)

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2022.2 English
  1. To run synthesis, simply click the C Synthesis toolbar button.

    The C Synthesis dialog box is displayed.

    Run C Synthesis

  2. Click OK.

    The synthesis command runs, and writes a transcript in the Console view. Examine the transcript to see what steps the tool takes during synthesis. The following list describes some of the steps listed:

    • Project and solution initialization loads source and constraints files, and configures the active solution for synthesis.

    • Start compilation reads source files into memory.

    • Interface detection and setup reviews and generates port and block interfaces for the function.

    • Burst read and write analysis for ports/interfaces.

    • Compiler transforms code to operations.

    • Performs Synthesizeability checks.

    • Automatic pipelining of loops at tripcount threshold.

    • Unrolling loops, both automatic and user-directed.

    • Balance expressions using associative and commutative properties.

    • Loop flattening to reduce loop hierarchy.

    • Partial write detection (writing part of a memory word)

    • Finish architecture synthesis, start scheduling.

    • End scheduling, generate RTL code.

    • Report FMax and loop constraint status.

    The Vitis HLS tool also automatically inlines small functions, dissolving the logic into the higher-level calling functions, and pipelines small loops with limited iterations. These features are configurable by user directives or pragmas.

  3. After synthesis completes, the Synthesis Summary report displays as shown in the following figure. Review the results.

    Synthesis Summary Report

    Notice that the various sub-functions from the Pre-synthesis control flow diagram are no longer reported in the synthesis results. This is because the tool has inlined these functions automatically. You can disable the inlining of specific functions by adding the INLINE OFF pragma or directive for the function, or by adding the DATAFLOW optimization to the design, which you will be doing later in this tutorial.

    The Vitis HLS tool also automatically pipelined loops that have fewer than a specified number of iterations. Pipelining loops with fewer than 64 iterations is the default setting. When pipelining, the tool tries to achieve an II of 1. The II is the number of clock cycles before the next iteration of the loop is processed. When pipelining the loop with II=1, you want the next iteration to start at the next clock cycle.