Using the Netlist Insertion Method to Debug a Design - 2022.1 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)

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2022.1 English

In this lab, you will mark signals for debug in the source HDL as well as the post synthesis netlist. Then you will create an Integrated Logic Analyzer (ILA) core and take the design through implementation. Finally, you will use the Vivado® tool to connect to the KC705 target board and debug your design with the Vivado Integrated Logic Analyzer.