Vivado Design Suite Tutorial: Programming and Debugging (UG936) - 2022.1 English - UG936

Document ID: UG936
Release Date: 2022-05-20
Version: 2022.1 English

Debugging in Vivado Tutorial
Navigating Content by Design Process
Objectives
Getting Started
Setup Requirements
Tutorial Design Components
Board Support and Pinout Information
Design Files
Connecting the Boards and Cables
Using the Netlist Insertion Method to Debug a Design
Step 1: Creating a Project with the Vivado New Project Wizard
Step 2: Synthesizing the Design
Step 3: Probing and Adding Debug IP
Adding Debug Nets to the Project
Running the Set Up Debug Wizard
Step 4: Implementing and Generating Bitstream
Using the HDL Instantiation Method to Debug a Design
Step 1: Creating a Project with the Vivado New Project Wizard
Step 2: Synthesize Implement and Generate Bitstream
Using a VIO Core to Debug a Design in Vivado Design Suite
Step 1: Creating a Project with the Vivado New Project Wizard
Step 2: Synthesize, Implement, and Generate the Bitstream
Using the Synplify Pro Synthesis Tool and Vivado Design Suite to Debug a Design
Step 1: Create a Synplify Pro Project
Step 2: Synthesize the Synplify Project
Step 3: Create DCPs for the Black Box Created in Synplify Pro
Step 4: Create a Post Synthesis Project in Vivado IDE
Step 5: Add More Debug Nets to the Project
Running the Set Up Debug Wizard
Step 6: Implementing the Design and Generating the Bitstream
Using the Vivado Logic Analyzer to Debug Hardware
Step 1: Verifying Operation of the Sine Wave Generator
Target Board and Server Set Up
Using the Vivado Integrated Logic Analyzer
Verifying Sine Wave Activity
Displaying the Sine Wave
Correcting Display of the Sine Wave
Step 2: Debugging the Sine Wave Sequencer State Machine (Optional)
Sine Wave Sequencer State Machine Overview
Viewing the State Machine Glitch
Fixing the Signal Glitch and Verifying the Correct State Machine Behavior
Verifying the VIO Core Activity (Only Applicable to Lab 3)
Using the ECO Flow to Replace Debug Probes Post Implementation
Debugging Designs Using the Incremental Compile Flow
Procedure
Step 1: Opening the Example Design and Adding a Debug Core
Step 2: Compiling the Reference Design
Step 3: Create New Runs
Step 4: Making Incremental Debug Changes
Step 5: Running Incremental Compile
Conclusion
Using the Vivado Serial Analyzer to Debug Serial Links
Design Description
Step 1: Creating, Customizing, and Generating an IBERT Design
Step 2: Adding an IBERT Core to the Vivado Project
Step 3: Synthesize, Implement and Generate Bitstream for the IBERT Design
Step 4: Interact with the IBERT Core Using Serial I/O Analyzer
Using the Vivado ILA Core to Debug JTAG-AXI Transactions
Design Description
Step 1: Creating a New Vivado Project and Generating the IP Integrator Design with JTAG-to-AXI and System ILA
Step 2: Program the KC705 Board and Interact with the JTAG to AXI Master Core
Step 3: Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction
Using the Vivado Serial Analyzer to Debug PS-GTR Serial Links
IBERT PS-GTR Flow
Step 1: Generating a Zynq UltraScale+ MPSoC PS Xilinx Support Archive
Step 2: Using Xilinx Software Command-line Tool Flow to Generate a First Stage Boot Loader
Step 3: ZCU102 Board Settings
Using FSBL with Serial I/O Analyzer to Bring Up IBERT PS-GTR
Troubleshooting
Known Issues
Notes
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Revision History
Please Read: Important Legal Notices

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