- From the Program and Debug drop-down list, in Flow Navigator, click
Generate Bitstream. This will
synthesize, implement and generate a bitstream for the design.
- The No Implementation Results Available dialog box appears. Click Yes. In the Launch Runs dialog box, accept all of the default settings (Launch runs on local host) and click OK.
- After bitstream generation completes, the Bitstream Generation Completed dialog box appears. Open Implemented Design is selected by default. Click OK.
- In the Design Timing Summary window, ensure that all timing constraints are
met.
- Proceed to Using the Vivado Logic Analyzer to Debug Hardware chapter to complete the rest of this lab.