Hardware Emulation - 2021.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2021.1 English

Hardware emulation simulates a complete Versal ACAP system composed of the AI Engine, PS, and PL. Using the Vitis software platform, you can integrate blocks and functions targeting all three compute domains. The Vitis linker automatically generates a complete co-simulation setup involving RTL, SystemC, and QEMU models:

  • Embedded software code running on the PS is emulated using QEMU.
  • Code running on the AI Engines is emulated using the SystemC AI Engine simulator.
  • User PL kernels are simulated as RTL code.
  • IP blocks in the hardware platform are simulated either as RTL or SystemC TLM, based on the types of models available or selected.

As a result, the abstraction of the Vitis hardware emulation is very close to but not fully cycle-accurate. Some details of the Versal ACAP platform are abstracted with TLM models for simulation speed purposes.

The scope of the Vitis hardware emulation also defines its purpose. Hardware emulation allows you to simulate the entire design and test the interactions between the PL, PS, and AI Engine prior to implementation. Because hardware emulation provides full debug visibility into all aspects of the application, it is easier to debug complex problems in this environment than in real hardware.

Hardware emulation is available through the Vitis unified software platform. For more information, see the Vitis Accelerated Software Development Flow Documentation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416) and the Versal ACAP AI Engine Programming Environment User Guide (UG1076).

Note: Hardware emulation is only possible in the platform-based design flow.