Estimating Power Throughout the Flow - 2021.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

Document ID
Release Date
2021.1 English

As your design flow progresses through synthesis and implementation, you must regularly monitor and verify the power consumption to be sure that thermal dissipation remains within budget, that the board voltage regulators remain within their current operating limits and the design stays within any system power limits. You can then take prompt remedial actions if the power approaches your budget too closely.

Specify a power budget to report the power margin using the XDC constraint:

set_operating_conditions -design_power_budget <value in watts>

This value is used by the report_power command. The difference between the calculated on-chip power and the power budget is the power margin, which is displayed in red in the Vivado IDE if the power budget is exceeded. This makes it easier to monitor power consumption throughout the flow.

The accuracy of the power estimates varies depending on the design stage when the power is estimated. To estimate power post-synthesis through implementation, run the report_power command, or open the Power Report in the Vivado IDE.

Post Synthesis
The netlist is mapped to the actual resources available in the target device.
Post Placement
The netlist components are placed into the actual device resources. With this packing information, the final logic resource count and configuration becomes available. This accurate data can be exported to the Xilinx® Power Estimator spreadsheet. This allows you to:
  • Perform what-if analysis in XPE.
  • Provide the basis for accurately filling in the spreadsheet for future designs with similar characteristics.
Post Routing
After routing is complete all the details about routing resources used and exact timing information for each path in the design are defined.